The disclosures herein relate generally to processors, and more specifically, to processors that employ instruction issue queue dependency management for store instructions.
Modern information handling systems (IHSs) often execute instruction out-of-order to achieve greater processing efficiency. Because out-of-order instruction handling is common in modern IHSs, processors typically track the dependencies between instructions in an issue queue such as a unified issue queue (UIQ). Many issue queues store respective single instructions in the particular locations that require individual reads and writes. However, a unified issue queue (UIQ) provides multiple queues for parallel instruction reads and writes. A particular instruction may not issue from the issue queue until dependencies for that particular instruction are met. These dependencies may include data dependencies and address dependencies. A particular instruction may issue to an execution unit when the processor determines that data dependency, address dependency, or other dependency requirements are met. That particular instruction may issue to an execution unit within the processor for further processing.
Vector scalar unit (VSU) store instructions are a type of instruction that involve operations relating to binary floating point instructions. The VSU is responsible for all vector and floating point instructions. During instruction decoding, a decode unit may identify instructions or internal operations (IOPs) that require execution by a special VSU type of execution unit (EU). Instructions or IOPs that require a VSU EU include VSU store instructions, VSX instructions, and other binary floating point instructions. VSU store instructions may exhibit data, address, and other dependencies. VSU store instructions in the issue queue may issue when their data dependencies, address dependencies, or other dependencies clear. VSU store and other instructions may group into IOP groups that share a common relationship within processor 200 instructions.